Modern integrated circuits (ICs) are developed through the use of hardware description languages (HDLs). HDLs such as VERILOG, VHDL, and the like allow developers to create software-based representations of circuit designs. One advantage of using an HDL is the potential for code reuse from one design to another. This concept has been realized with the commercial availability of intellectual property (IP) cores.
In general, an IP core (hereinafter core or module) refers to a software representation of a semiconductor component that provides a processing function. Different varieties of cores exist. For example, some cores can provide basic functions. These cores can be included in a circuit design or, alternatively, can be used as subcomponents within a larger, more complex core. Another variety of cores can function as a logic bridge to software-based bus objects such as Peripheral Component Interconnect (PCI) and/or Advanced Microcontroller Bus Architecture (AMBA) busses.
Some cores are highly configurable and prior to release undergo extensive testing to verify whether or not the core is functionally correct. A common approach to verification of a core is with a testbench. A testbench, also referred to as a verification environment, provide test stimuli and verify the behavior of a design under test, in this case one or more cores. Generating a testbench involves describing the connections, events, and test vectors for different combinations of transactions involving the core(s). A testbench also refers to the code used to create a pre-determined input sequence to the cores, as well as the code responsible for observing the response.
A core may undergo a number of transformations in the process of incorporating the core into a larger design and implementing the final product. Initially, the core may be customized according to the requirements of the target application. For example, the core may be customized in terms of data width, data rate, etc. The customization of an IP core may be governed by a specific set of parameters and rules that define how the parameters are translated into values for the core's HDL parameters. In later stages, the core may be synthesized, and the resulting netlist optimized, placed and routed.
At each stage it would be desirable to verify that no errors have been introduced into the core. If an error is discovered only after the circuit has been implemented, identifying the source of and fixing the error may be extremely expensive and time consuming. Also, in some instances, extra licensing fees may be incurred for the use of different simulation tools at different stages of the design process.